library verilog;
use verilog.vl_types.all;
entity PWM_COUNTER is
    generic(
        cnt_mod_value   : vl_logic_vector(0 to 6) := (Hi1, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0);
        cnt_mod_compare_value: vl_notype
    );
    port(
        i_pwm_clk       : in     vl_logic;
        i_sys_rst       : in     vl_logic;
        o_pwm_val       : out    vl_logic_vector(6 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of cnt_mod_value : constant is 1;
    attribute mti_svvh_generic_type of cnt_mod_compare_value : constant is 3;
end PWM_COUNTER;
